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19-2722; Rev 0; 04/03
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
General Description
The MAX1266/MAX1268 low-power, 12-bit analog-todigital converters (ADCs) feature a successive-approximation ADC, automatic power-down, fast wake-up (2s), an on-chip clock, +2.5V internal reference, and a high-speed 12-bit parallel interface. They operate with a single +5V analog supply. Power consumption is only 10mW at the maximum sampling rate of 420ksps. Two software-selectable powerdown modes enable the MAX1266/MAX1268 to be shut down between conversions; accessing the parallel interface returns them to normal operation. Powering down between conversions can reduce supply below 10A at lower sampling rates. Both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differential operation. In single-ended mode, the MAX1266 has six input channels and the MAX1268 has two (three input channels and one input channel, respectively, when in pseudo-differential mode). Excellent dynamic performance and low power, combined with ease of use and small package size, make these converters ideal for battery-powered and dataacquisition applications or for other circuits with demanding power-consumption and space requirements. The MAX1266 is offered in a 28-pin QSOP package, while the MAX1268 is available in a 24-pin QSOP. For pin-compatible +3V, 12-bit versions, see the MAX1265/MAX1267. o 12-Bit Resolution, 0.5 LSB Linearity o Single +5V Operation o Internal +2.5V Reference o Software-Configurable Analog Input Multiplexer 6-Channel Single Ended/ 3-Channel Pseudo-Differential (MAX1266) 2-Channel Single Ended/ 1-Channel Pseudo-Differential (MAX1268) o Software-Configurable Unipolar/Bipolar Analog Inputs o Low Current 2.8mA (420ksps) 1.0mA (100ksps) 400A (10ksps) 2A (Shutdown) o Internal 6MHz Full-Power Bandwidth Track/Hold o Parallel 12-Bit Interface o Small Footprint 28-Pin QSOP (MAX1266) 24-Pin QSOP (MAX1268)
Features
MAX1266/MAX1268
Pin Configurations
TOP VIEW
Applications
Industrial Control Systems Energy Management Data-Acquisition Systems Data Logging Patient Monitoring Touch Screens
D9 1 D8 2 D7 3 D6 4 D5 5
24 D10 23 D11 22 VDD 21 REF 20 REFADJ
Ordering Information
PART MAX1266ACEI MAX1266BCEI MAX1266AEEI MAX1266BEEI MAX1268ACEG MAX1268BCEG TEMP RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C 0C to +70C 0C to +70C PIN-PACKAGE 28 QSOP 28 QSOP 28 QSOP 28 QSOP 24 QSOP 24 QSOP 24 QSOP 24 QSOP INL (LSB) 0.5 1 0.5 1 0.5 1 0.5 1
D4 6 D3 7 D2 8 D1 9 D0 10 INT 11 RD 12
MAX1268
19 GND 18 COM 17 CH0 16 CH1 15 CS 14 CLK 13 WR
QSOP Pin Configurations continued at end of data sheet. Typical Operating Circuits appear at end of data sheet.
MAX1268AEEG -40C to +85C MAX1268BEEG -40C to +85C
________________________________________________________________ Maxim Integrated Products
1
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V CH0-CH5, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND.................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.3V to +6V Digital Outputs (D0-D11, INT) to GND.......-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) 24-Pin QSOP (derate 9.5mW/C above +70C)..........762mW 28-Pin QSOP (derate 8.0mW/C above +70C)..........667mW Operating Temperature Ranges MAX1266_C_ _/MAX1268_C_ _ .........................0C to +70C MAX1266_E_ _/MAX1268_E_ _ ......................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +5V 10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient Channel-to-Channel Offset Matching Signal-to-Noise Plus Distortion Total Harmonic Distortion (Including 5th-Order Harmonic) Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk Full-Linear Bandwidth Full-Power Bandwidth CONVERSION RATE External clock mode Conversion Time (Note 5) T/H Acquisition Time Aperture Delay Aperture Jitter External Clock Frequency Duty Cycle 2 fCLK tCONV tACQ External acquisition or external clock mode External acquisition or external clock mode Internal acquisition/internal clock mode 0.1 30 25 <50 <200 7.6 70 External acquisition/internal clock mode Internal acquisition/internal clock mode 2.1 2.5 3.2 3.0 3.6 3.5 4 400 ns ns ps MHz % s SINAD THD SFDR IMD fIN1 = 49kHz, fIN2 = 52kHz fIN = 175kHz (Note 4) SINAD > 68dB -3dB rolloff -80 76 -78 350 6 67 (Note 3) 2.0 0.2 RES INL DNL MAX126_A MAX126_B No missing codes overtemperature 12 0.5 1 1 4 4 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (fIN(sine wave) = 50kHz, VIN = 2.5VP-P, 420ksps, external fCLK = 7.6MHz, bipolar input mode) 70 -80 dB dB dB dB dB kHz MHz
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +5V 10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ANALOG INPUTS Analog Input Voltage Range Single Ended and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Temperature Coefficient REFADJ Input Range REFADJ High Threshold Load Regulation Capacitive Bypass at REFADJ Capacitive Bypass at REF EXTERNAL REFERENCE AT REF REF Input Voltage Range REF Input Current DIGITAL INPUTS AND OUTPUTS Input Voltage High Input Voltage Low Input Hysteresis Input Leakage Current Input Capacitance Output Voltage Low Output Voltage High Tri-State Leakage Current Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage VDD Operating mode, fSAMPLE = 420ksps Standby mode Shutdown mode Power-Supply Rejection PSR VDD = 5V 10%, full-scale input Internal reference External reference Internal reference External reference 4.5 3.3 2.8 1.0 0.5 2 0.3 5.5 3.6 3.1 1.2 0.8 10 0.9 A mV mA V VIH VIL VHYS IIN CIN VOL VOH ILEAKAGE COUT ISINK = 1.6mA ISOURCE = 1mA CS = VDD CS = VDD VDD - 0.5 0.1 15 1 VIN = 0 or VDD 200 0.1 15 0.4 1 4.0 0.8 V V mV A pF V V A pF VREF IREF VREF = 2.5V, fSAMPLE = 420ksps Shutdown mode 1.0 200 VDD + 50mV 300 2 V A 4.7 TCREF For small adjustments To power down the internal reference 0 to 0.5mA output load (Note 7) VDD - 1 0.2 0.01 1 10 2.49 2.5 15 20 100 2.51 V mA ppm/C mV V mV/mA F F CIN Unipolar, VCOM = 0 VIN Bipolar, VCOM = VREF / 2 On-/off-leakage current, VIN = 0 or VDD 0 -VREF/2 0.01 12 VREF +VREF/2 1 V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1266/MAX1268
Positive Supply Current
IDD IDD
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
TIMING CHARACTERISTICS
(VDD = +5V 10%, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 7.6MHz (50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CLK Period CLK Pulse Width High CLK Pulse Width Low Data Valid to WR Rise Time WR Rise to Data Valid Hold Time WR to CLK Fall Setup Time CLK Fall to WR Hold Time CS to CLK or WR Setup Time CLK or WR to CS Hold Time CS Pulse Width WR Pulse Width CS Rise to Output Disable RD Rise to Output Disable RD Fall to Output Data Valid RD Fall to INT High Delay CS Fall to Output Data Valid SYMBOL tCP tCH tCL tDS tDH tCWS tCWH tCSWS tCSWH tCS tWR tTC tTR tDO tINT1 tDO2 (Note 8) CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CONDITIONS MIN 132 40 40 40 0 60 40 40 0 100 60 10 10 10 60 40 50 50 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Tested at VDD = +5V, COM = GND, unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 3: Offset nulled. Note 4: On channel is grounded; sine wave applied to off channels. Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has a 50% duty cycle. Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD. Note 7: External load should not change during conversion for specified accuracy. Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
VDD 3k DOUT 3k CLOAD 20pF DOUT CLOAD 20pF
a) High-Z to VOH and VOL to VOH
b) High-Z to VOL and VOH to VOL
Figure 1. Load Circuits for Enable/Disable Times
4
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Typical Operating Characteristics
(VDD = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25C, unless otherwise noted.)
MAX1266/MAX1268
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1266/68 toc01
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX1266/68 toc02A
SUPPLY CURRENT vs. SAMPLE FREQUENCY
MAX1266/68 toc02B
0.5 0.4 0.3 0.2
0.5 0.4 0.3 0.2 DNL (LSB)
10,000 WITH INTERNAL REFERENCE 1000 IDD (A)
INL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1000 2000 3000 4000 5000 DIGITAL OUTPUT CODE
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1000 2000 3000 4000 5000 DIGITAL OUTPUT CODE
100
10 WITH EXTERNAL REFERENCE 0 0.1 1 10 100 1k 10k 100k 1M fSAMPLE (Hz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
RL = CODE = 101010100000
MAX1266/68 toc03
SUPPLY CURRENT vs. TEMPERATURE
MAX1266/68 toc04
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1266/68 toc05
2.2
2.3 2.2 2.1
RL = CODE = 101010100000
990 980 STANDBY IDD (A) 970 960 950 940 930
2.1 IDD (mA)
2.0
IDD (mA)
2.0 1.9
1.9 1.8 1.8 4.50 4.75 5.00 VDD (V) 5.25 5.50 1.7 -40 -15 10 35 60 85 TEMPERATURE (C)
4.50
4.75
5.00 VDD (V)
5.25
5.50
STANDBY CURRENT vs. TEMPERATURE
MAX1266/68 toc06
POWER-DOWN CURRENT vs. SUPPLY VOLTAGE
MAX1266/68 toc07
POWER-DOWN CURRENT vs. TEMPERATURE
MAX1266/68 toc08
990 980 STANDBY IDD (A) 970 960 950 940 930 -40 -15 10 35 60
3.0
2.2
POWER-DOWN IDD (A)
2.0
POWER-DOWN IDD (A) 4.50 4.75 5.00 VDD (V) 5.25 5.50
2.5
2.1
2.0
1.5
1.9
1.0 85 TEMPERATURE (C)
1.8 -40 -15 10 35 60 85 TEMPERATURE (C)
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
Typical Operating Characteristics (continued)
(VDD = +5V, VREF = +2.500V, fCLK = 7.6MHz, CL = 20pF, TA = +25C, unless otherwise noted.)
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1266/68 toc09
REFERENCE VOLTAGE vs. TEMPERATURE
MAX1266/68 toc10
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1266/68 toc11
2.53
2.53
1.0
2.52
2.52
VREF (V)
VREF (V)
2.51
2.51
OFFSET ERROR (LSB) -40 -15 10 35 60 85
0.5
0
2.50
2.50
2.49
2.49
-0.5
2.48 4.50 4.75 5.00 VDD (V) 5.25 5.50
2.48 TEMPERATURE (C)
-1.0 4.50 4.75 5.00 VDD (V) 5.25 5.50
OFFSET ERROR vs. TEMPERATURE
MAX1266/68 toc12
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1266/68 toc13
GAIN ERROR vs. TEMPERATURE
MAX1266/68 toc14
2
2
2.0
OFFSET ERROR (LSB)
1
1 GAIN ERROR (LSB)
1.5 GAIN ERROR (LSB)
0
0
1.0
-1
-1
0.5
-2 -40 -15 10 35 60 85 TEMPERATURE (C)
-2 4.50 4.75 5.00 VDD (V) 5.25 5.50
0 -40 -15 10 35 60 85 TEMPERATURE (C)
FFT PLOT
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 -140 0 200 400 600 800 1000 FREQUENCY (kHz) VDD = 5V fIN = 50kHz fSAMPLE = 400ksps
MAX1266/68 toc15
20
6
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Pin Description
PIN NAME MAX1266 1 2 3 4 5 6 7 8 9 10 11 12 MAX1268 1 2 3 4 5 6 7 8 9 10 11 12 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 INT RD Tri-State Digital Output (D9) Tri-State Digital Output (D8) Tri-State Digital I/O Line (D7) Tri-State Digital I/O Line (D6) Tri-State Digital I/O Line (D5) Tri-State Digital I/O Line (D4) Tri-State Digital I/O Line (D3) Tri-State Digital I/O Line (D2) Tri-State Digital I/O Line (D1) Tri-State Digital I/O Line (D0) INT goes low when the conversion is complete and output data is ready. Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on the data bus. Active-Low Write Select. When CS is low in the internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low in external acquisition mode, the first rising edge on WR ends acquisition and starts a conversion. Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In internal clock mode, connect this pin to either VDD or GND. Active-Low Chip Select. When CS is high, digital outputs (D11-D0) are high impedance. Analog Input Channel 5 Analog Input Channel 4 Analog Input Channel 3 Analog Input Channel 2 Analog Input Channel 1 Analog Input Channel 0 Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and must be stable to 0.5 LSB during conversion. Analog and Digital Ground Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01F capacitor. When using an external reference, connect REFADJ to VDD to disable the internal bandgap reference. FUNCTION
MAX1266/MAX1268
13
13
WR
14 15 16 17 18 19 20 21 22 23 24
14 15 -- -- -- -- 16 17 18 19 20
CLK CS CH5 CH4 CH3 CH2 CH1 CH0 COM GND REFADJ
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
Pin Description (continued)
PIN NAME MAX1266 25 26 27 28 MAX1268 21 22 23 24 REF VDD D11 D10 Bandgap Reference Buffer Output/External Reference Input. Add a 4.7F capacitor to GND when using the internal reference. Analog +5V Power Supply. Bypass with a 0.1F capacitor to GND. Tri-State Digital Output (D11) Tri-State Digital Output (D10) FUNCTION
REF
REFADJ 17k
AV = 2.05 (CH5) (CH4) (CH3) (CH2) CH1 CH0 COM
1.22V REFERENCE
ANALOG INPUT MULTIPLEXER
T/H CHARGE REDISTRIBUTION 12-BIT DAC 12 SUCCESSIVEAPPROXIMATION REGISTER COMP
CLK
CLOCK
CS WR RD INT
CONTROL LOGIC AND LATCHES 12 TRI-STATE, BIDIRECTIONAL I/O INTERFACE D0-D11 12-BIT DATA BUS
MAX1266 MAX1268
VDD GND
( ) ARE FOR MAX1266 ONLY.
Figure 2. Simplified Functional Diagram
_______________Detailed Description
Converter Operation
The MAX1266/MAX1268 ADCs use a successive-approximation (SAR) conversion technique and an input
8
track/hold (T/H) stage to convert an analog input signal to a 12-bit digital output. This output format provides easy interface to standard microprocessors (Ps). Figure 2 shows the simplified internal architecture of the MAX1266/ MAX1268.
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Single-Ended and Pseudo-Differential Operation
The sampling architecture of the ADC's analog comparator is illustrated in the equivalent input circuits of Figure 3. In single-ended mode, IN+ is internally switched to channels CH0-CH5 for the MAX1266 (Figure 3a) and to CH0-CH1 for the MAX1268 (Figure 3b), while IN- is switched to COM (Table 2). In differential mode, IN+ and IN- are selected from analog input pairs (Table 3) and are internally switched to either of the analog inputs. This configuration is pseudo-differential to the effect that only the signal at IN+ is sampled. The return side (IN-) must remain stable within 0.5 LSB (0.1 LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.1F capacitor from IN- (the selected input) to GND.
MAX1266/MAX1268
12-BIT CAPACITIVE DAC VREF CHOLD INPUT 12pF MUX - + COMPARATOR ZERO CH0 CH1 VREF
12-BIT CAPACITIVE DAC
CH0 CH1 CH2 CH3 CH4 CH5 COM
CHOLD INPUT 12pF MUX - +
COMPARATOR ZERO
CSWITCH TRACK
RIN 800 HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
CSWITCH TRACK
RIN 800 HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL.
T/H SWITCH
T/H SWITCH COM
SINGLE-ENDED MODE: IN+ = CH0-CH5, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS CH0/CH1, CH2/CH3, AND CH4/CH5
SINGLE-ENDED MODE: IN+ = CH0-CH1, IN- = COM DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIR CH0/CH1
Figure 3a. MAX1266 Simplified Input Structure
Figure 3b. MAX1268 Simplified Input Structure
Table 1. Control-Byte Functional Description
BIT NAME FUNCTIONAL DESCRIPTION PD1 and PD0 select the various clock and power-down modes. 0 D7, D6 PD1, PD0 0 1 1 D5 ACQMOD 0 1 0 1 Full power-down mode. Clock mode is unaffected. Standby power-down mode. Clock mode is unaffected. Normal operation mode. Internal clock mode selected. Normal operation mode. External clock mode selected.
ACQMOD = 0: Internal acquisition mode ACQMOD = 1: External acquisition mode SGL/DIF = 0: Pseudo-differential analog input mode SGL/DIF = 1: Single-ended analog input mode In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage difference between two channels is measured (Tables 2 and 4). UNI/BIP = 0: Bipolar mode UNI/BIP = 1: Unipolar mode In unipolar mode, an analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. Address bits A2, A1, A0 select which of the 6/2 (MAX1266/MAX1268) channels is to be converted (Tables 2 and 3). 9
D4
SGL/DIF
D3
UNI/BIP
D2, D1, D0
A2, A1, A0
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
Table 2. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 CH0 + + + + + + CH1 CH2* CH3* CH4* CH5* COM -
*Channels CH2-CH5 apply to MAX1266 only.
Table 3. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2 0 0 0 0 1 1 A1 0 0 1 1 0 0 A0 0 1 0 1 0 1 CH0 + + + + + + CH1 CH2* CH3* CH4* CH5*
*Channels CH2-CH5 apply to MAX1266 only.
During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node zero at the comparator's positive input. The capacitive digital-toanalog converter (DAC) adjusts during the remainder of the conversion cycle to restore node 0 to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a 12pF [(VIN+ - VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
If an analog input voltage exceeds the supplies by more than 50mV, limit the forward-bias input current to 4mA.
Track/Hold
The MAX1266/MAX1268 T/H stage enters its tracking mode on the rising edge of WR. In external acquisition mode, the part enters its hold mode on the next on rising edge of WR. In internal acquisition mode, the part enters its hold mode on the fourth falling edge of clock after writing the control byte. Note that, in internal clock mode, this is approximately 1s after writing the control byte. In single-ended operation, IN- is connected to COM and the converter samples the positive (+) input. In pseudo-differential operation, IN- connects to the negative (-) input, and the difference of |(IN+) - (IN-)| is sampled. At the beginning of the next conversion, the positive input connects back to IN+ and C HOLD charges to the input signal. The time required for the T/H stage to acquire an input signal depends on how quickly its input capacitance is charged. If the input signal's source impedance is high,
Analog Input Protection
Internal protection diodes, which clamp the analog input to VDD and GND, allow each input channel to swing within (GND - 300mV) to (VDD + 300mV) without damage. However, for accurate conversions near full scale, both inputs must not exceed (VDD + 50mV) or be less than (GND - 50mV).
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
the acquisition time lengthens and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal, and is also the minimum time required for the signal to be acquired. Calculate this with the following equation: tACQ = 9(RS + RIN)CIN where RS is the source impedance of the input signal, RIN (800) is the input resistance, and CIN (12pF) is the ADC's input capacitance. Source impedances below 3k have no significant impact on the MAX1266/ MAX1268s' AC performance. Higher source impedances can be used if a 0.01F capacitor is connected to the individual analog inputs. Together with the input impedance, this capacitor forms an RC filter, limiting the ADC's signal bandwidth. ends (Figure 4). Note that, when the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. Internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode. External Acquisition Use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0 (all other bits in control byte unchanged), terminates acquisition and starts conversion on WR rising edge (Figure 5). The address bits for the input multiplexer must have the same values on the first and second write pulse. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see Power-Down Modes section). Changing other bits in the control byte corrupts the conversion.
MAX1266/MAX1268
Input Bandwidth
The MAX1266/MAX1268 T/H stage offers a 350kHz fulllinear and a 6MHz full-power bandwidth. This makes it possible to digitize high-speed transients and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the MAX1266/MAX1268 to flag the P when the conversion has ended and a valid result is available. INT goes low when the conversion is complete and the output data is ready (Figures 4 and 5). It returns high on the first read cycle or if a new control byte is written.
Starting a Conversion
Initiate a conversion by writing a control byte, which selects the multiplexer channel and configures the MAX1266/MAX1268 for either unipolar or bipolar operation. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD (acquisition mode) bit in the input control byte (Table 1) offers two options for acquiring the signal: an internal and an external acquisition. The conversion period lasts for 13 clock cycles in either the internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle aborts the conversion and starts a new acquisition interval. Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval (three external clock cycles or approximately 1s in internal clock mode)
Selecting Clock Mode
The MAX1266/MAX1268 operate with either an internal or an external clock. Control bits D6 and D7 select either internal or external clock mode. The part retains the last-requested clock mode if a power-down mode is selected in the current input word. For both internal and external clock mode, internal or external acquisition can be used. At power-up, the MAX1266/MAX1268 enter the default external clock mode. Internal Clock Mode Select internal clock mode to release the P from the burden of running the SAR conversion clock. Bit D7 of the control byte must be set to 1 and bit D6 must be set to zero. The internal clock frequency is then selected, resulting in a conversion time of 3.6s. When using the internal clock mode, tie the CLK pin either high or low to prevent the pin from floating.
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
tCS
CS tCSWS WR tDS D11-D0 CONTROL BYTE tWR
tACQ tCSWH
tCONV
tDH
ACQMOD = 0 INT
tINT1
RD
tD0 HIGH-Z DOUT VALID DATA
tTR HIGH-Z
Figure 4. Conversion Timing Using Internal Acquisition Mode
tCS
CS tCSWS WR tDS D11-D0 CONTROL BYTE ACQMOD = 1 tDH CONTROL BYTE ACQMOD = 0 tNT1 tWR tACQ tCSLOH tCONV
INT
RD tD0 HIGH-Z DOUT VALID DATA tTR HIGH-Z
Figure 5. Conversion Timing Using External Acquisition Mode
12
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
External Clock Mode To select external clock mode, bits D6 and D7 of the control byte must be set to 1. Figure 6 shows the clock and WR timing relationship for internal (Figure 6a) and external (Figure 6b) acquisition modes with an external clock. For proper operation, a 100kHz to 7.6MHz clock frequency with 30% to 70% duty cycle is recommended. Operating the MAX1266/MAX1268 with clock frequencies lower than 100kHz is not recommended, because the resulting voltage droop across the hold capacitor in the T/H stage degrades performance.
Digital Interface
The input and output data are multiplexed on a tri-state parallel interface (I/O) that can easily be interfaced with standard Ps. The signals CS, WR, and RD control the write and read operations. CS represents the chipselect signal, which enables a P to address the MAX1266/MAX1268 as an I/O port. When high, CS disables the CLK, WR, and RD inputs and forces the interface into a high-impedance (high-Z) state.
MAX1266/MAX1268
ACQUISITION STARTS tCP CLK tCWS tCH WR ACQMOD = 0 tCWH CLK ACQUISITION STARTS tCL
ACQUISITION ENDS
CONVERSION STARTS
WR GOES HIGH WHEN CLK IS HIGH
ACQUISITION ENDS
CONVERSION STARTS
WR ACQMOD = 0 WR GOES HIGH WHEN CLK IS LOW
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS
CLK tDH WR ACQMOD = 1 WR GOES HIGH WHEN CLK IS HIGH ACQUISITION STARTS CLK tDH WR ACQMOD = 1 WR GOES HIGH WHEN CLK IS LOW ACQMOD = 0 tCWH ACQUISITION ENDS CONVERSION STARTS ACQMOD = 0 tCWS
Figure 6b. External Clock and WR Timing (External Acquisition Mode) ______________________________________________________________________________________ 13
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
Table 4. Control-Byte Format
D7 (MSB) PD1 D6 PD0 D5 ACQMOD D4 SGL/DIF D3 UNI/BIP D2 A2 D1 A1 D0 (LSB) A0
Input Format The control bit sequence is latched into the device on pins D7-D0 during a write command. Table 4 shows the control-byte format. Output Data Format The 12-bit-wide output format for both the MAX1266/ MAX1268 is binary in unipolar mode and two's complement in bipolar mode. CS, RD, WR, INT, and the 12 bits of output data can interface directly to a 16-bit data bus. When reading the output data, CS and RD must be low.
VDD = +5V 50k 330k 50k 4.7F 0.01F MAX1266 MAX1268 REFADJ REF
Applications Information
Power-On Reset
When power is first applied, internal power-on reset circuitry activates the MAX1266/MAX1268 in external clock mode and sets INT high. After the power supplies stabilize, the internal reset time is 10s; no conversions should be attempted during this phase. When using the internal reference, 500s are required for VREF to stabilize.
Figure 7. Reference Adjustment with External Potentiometer
Using the REFADJ input makes buffering the external reference unnecessary. The REFADJ input impedance is typically 17k. When applying an external reference to REF, disable the internal reference buffer by connecting REFADJ to VDD. The DC input resistance at REF is 25k. Therefore, an external reference at REF must deliver up to 200A DC load current during a conversion and have an output impedance less than 10. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor.
Internal and External Reference
The MAX1266/MAX1268 can be used with an internal or external reference voltage. An external reference can be connected directly to REF or REFADJ. An internal buffer is designed to provide +2.5V at REF for both devices. The internally trimmed +1.22V reference is buffered with a +2.05V/V gain. Internal Reference The full-scale range with the internal reference is +2.5V with unipolar inputs and 1.25V with bipolar inputs. The internal reference buffer allows for small adjustments (100mV) in the reference voltage (Figure 7). Note: The reference buffer must be compensated with an external capacitor (4.7F min) connected between REF and GND to reduce reference noise and switching spikes from the ADC. To further minimize reference noise, connect a 0.01F capacitor between REFADJ and GND. External Reference With the MAX1266/MAX1268, an external reference can be placed at either the input (REFADJ) or the output (REF) of the internal-reference buffer amplifier.
Power-Down Modes
To save power, place the converter in a low-current shutdown state between conversions. Select standby mode or shutdown mode using bits D6 and D7 of the control byte (Tables 1 and 4). In both software powerdown modes, the parallel interface remains active, but the ADC does not convert. Standby Mode While in standby mode, the supply current is typically 1mA. The part powers up on the next rising edge of WR and is ready to perform conversions. This quick turn-on time allows the user to realize significantly reduced power consumption for conversion rates below 420ksps.
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
Table 5. Full Scale and Zero Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE Full scale Zero scale -- VREF + COM COM -- Zero scale Negative full scale BIPOLAR MODE Positive full scale VREF/2 + COM COM -VREF/2 + COM
OUTPUT CODE FS = REF + COM ZS = COM 1 LSB = 100 . . . 010 100 . . . 001 100 . . . 000 011 . . . 111 011 . . . 110 011 . . . 101 REF 4096 FULL-SCALE TRANSITION
OUTPUT CODE FS = REF + COM 2 ZS = COM -REF + COM 2 REF 1 LSB = 4096 -FS =
111 . . . 111 111 . . . 110
011 . . . 111 011 . . . 110
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
000 . . . 001 000 . . . 000 01 (COM) 2 2048 INPUT VOLTAGE (LSB) FS - 3/2 LSB FS
100 . . . 001 100 . . . 000 - FS *COM VREF / 2 COM* INPUT VOLTAGE (LSB) +FS - 1 LSB
Figure 8. Unipolar Transfer Functions
Figure 9. Bipolar Transfer Functions
Shutdown Mode Shutdown mode turns off all chip functions that draw quiescent current, reducing the typical supply current to 2A immediately after the current conversion is completed. A rising edge on WR causes the MAX1266/ MAX1268 to exit shutdown mode and return to normal operation. To achieve full 12-bit accuracy with a 4.7F reference bypass capacitor, 500s is required after power-up. Waiting 500s in standby mode, instead of in full-power mode, can reduce power consumption by a factor of 3 or more. When using an external reference, only 50s is required after power-up. Enter standby mode by performing a dummy conversion with the control byte specifying standby mode. Note: Bypass capacitors larger than 4.7F between REF and GND result in longer power-up delays.
unipolar input/output (I/O) transfer function, and Figure 9 shows the bipolar I/O transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = (VREF / 4096).
Maximum Sampling Rate/ Achieving 475ksps
When running at the maximum clock frequency of 7.6MHz, the specified throughput of 420ksps is achieved by completing a conversion every 18 clock cycles: 1 write cycle, 3 acquisition cycles, 13 conversion cycles, and 1 read cycle. This assumes that the results of the last conversion are read before the next control byte is written. It is possible to achieve higher throughputs, up to 475ksps, by first writing a control byte to begin the acquisition cycle of the next conversion, then reading the results of the previous conversion from the bus. This technique (Figure 10) allows a conversion to be completed every 16 clock cycles. Note that the switching of the data bus during acquisi-
Transfer Function
Table 5 shows the full-scale voltage ranges for unipolar and bipolar modes. Figures 8 depicts the nominal
______________________________________________________________________________________
15
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WR RD
D7-D0
CONTROL WORD
STATE
Figure 10. Timing Diagram for Fastest Conversion
tion or conversion can cause additional supply noise, which can make it difficult to achieve true 12-bit performance.
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Wirewrap configurations are not recommended, since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 11) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply, VDD, could impair operation of the ADC's fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1F and 4.7F, located as close to the MAX1266/MAX1268s' power-supply pin as possible. Minimize capacitor lead length for best supply-noise rejection and add an attenuation resistor (5) if the power supply is extremely noisy.
;;
D11- D0 CONTROL WORD D11-D0 ACQUISITION CONVERSION ACQUISITION SAMPLING INSTANT SUPPLIES +5V +5V GND R* = 5 4.7F 0.1F VDD GND COM +5V DGND
MAX1266 MAX1268
*OPTIONAL
DIGITAL CIRCUITRY
Figure 11. Power-Supply and Grounding Connections
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420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1266/MAX1268 is measured using the endpoint method.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 log (SignalRMS / NoiseRMS)
MAX1266/MAX1268
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
THD = 20 x log V22 + V32 + V4 2 + V52 / V1
Aperture Delay
Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N-bits): SNR = (6.02 N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
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17
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1266/MAX1268
Typical Operating Circuits
CLK CLK
MAX1266 VDD
P CONTROL INPUTS CS WR RD D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CH5 CH4 CH3 CH2 CH1 CH0 COM GND INT REF REFADJ 0.1F
+5V +2.5V 4.7F P CONTROL INPUTS CS WR RD D11 D10 D9 D8 D7 D6 D5 ANALOG INPUTS D4 D3 D2 D1 D0
MAX1268 VDD
REF REFADJ INT 0.1F
+5V +2.5V 4.7F
OUTPUT STATUS
OUTPUT STATUS
CH1 CH0 COM GND ANALOG INPUTS
P DATA BUS
P DATA BUS
Pin Configurations (continued)
TOP VIEW
D9 1 D8 2 D7 3 D6 4 D5 5 D4 6 D3 7 D2 8 D1 9 D0 10 INT 11 RD 12 WR 13 CLK 14 28 D10 27 D11 26 VDD 25 REF 24 REFADJ
Chip Information
TRANSISTOR COUNT: 5781 SUBSTRATE CONNECTED TO GND
MAX1266
23 GND 22 COM 21 CH0 20 CH1 19 CH2 18 CH3 17 CH4 16 CH5 15 CS
QSOP 18 ______________________________________________________________________________________
420ksps, +5V, 6-/2-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX1266/MAX1268
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________19 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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